Detail for my sketch, RST_375us_dev.ino

/* February 2014
 * Tool to capture the raw V and I samples generated by the Atmega 328P processor
 * during one or more mains cycles.  The data is displayed on the Serial Monitor. 
 *
 * Voltage samples are displayed as 'v'
 * Current samples via CT1 are displayed as '1'
 *
 * The display is more compact if not every set of samples is shown.  This aspect
 * can be changed at the second of the two lines of code which contain a '%' character.  
 * 
 * February 2021
 * In the original version, data samples were obtained using the analogRead() function.  Now, 
 * they are obtained by the ADC being controlled by a hardware timer with a periodicity of 125 us,
 * hence a full set of 1 x V and 2 x I samples takes 375 us.  The same scheme for collecting 
 * data samples is found in many of my Mk2 PV Router sketches.
 * 
 * When used with an output stage that has zero-crossing detection, the signal at port D4 can 
 * be used to activate a load for just a single half main cycle.  The behaviour of the output signal 
 * from CT1 can then be studied in detail.  
 * 
 * The stream of raw data samples from any floating CT will always be distorted because the CT acts as 
 * a High Pass Filter.  This effect is only noticeable when the current that is being measured changes, 
 * such as when an electrical load is turned on or off.  This sketch includes additional software which 
 * compensates for this effect.  Similar compensation software has been introduced to the varous 
 * "fasterControl" sketches that now exist.
 *
 *      Robin Emley
 *      www.Mk2PVrouter.co.uk
 *      June 2021
 */